VLSI Design Styles

Various Design Styles

  • Programmable Logic Devices
    • Field Programmable Gate Array (FPGA)
    • Gate Array
  • Standard Cell (Semi-Custom Design)
  • Full-Custom Design

Field Programmable Gate Arrays (FPGAs)

What FPGAs Offer

  • User / Field Programmability.
  • An array of logic cells connected via routing channels.
  • Different types of cells:
    • Special I/O cells.
    • Logic cells (Mainly lookup tables (LUT) with associated registers).
  • Interconnection between cells:
    • Using SRAM based switches.
    • Using anti-fuse elements.

Ease of Use

  • FPGA chips are manufactured by a number of vendors:
    • Xilinx, Altera, Actel, etc.
    • Products vary widely in capability.
  • FPGA development boards and CAD software available from many sellers.
    • Allows rapid prototyping in laboratory.

FPGA Architecture and Components

  • A typical architecture consists of:
    • Configurable Logic Blocks (CLBs)
    • Programmable Interconnect
    • I/O Blocks (IOBs)

The Configurable Logic Block (CLB)

  • A CLB has two primary functionalities:
    • Two 4-input function generators
      • Implemented using Lookup Tables using 16x1 RAM.
      • Can also implement 16x1 memory.
    • Two 1-bit registers
      • Each can be configured as flip-flop or latch.
      • Independent clock polarity.
      • Synchronous and asynchronous Set / Reset.

Look Up Tables (LUT)

  • Combinatorial Logic is stored in 16x1 SRAM Look Up Tables (LUTs) in a CLB.
  • Capacity is limited by number of inputs, not complexity.
  • Choose to use each function generator as 4-input logic (LUT) or as high-speed RAM.

LUT Mapping

  • An example function: $f = A’.B + B’.C.D$
  • The mapping process:
    • Create the truth table of the 4-variable function.
    • Load the output column into the SRAM corresponding to the LUT.
    • Apply the function inputs to the LUT inputs.
  • Any 4-variable function can be realized.
  • Netlist to LUT mapping is an interesting design tradeoff between area and delay.

FPGA Routing

  • Fast Direct Interconnect – CLB to CLB
  • General Purpose Interconnect – Uses switch matrix

FPGA Design Flow

  • Design Entry
    • In schematic, VHDL, or Verilog.
  • Implementation
    • Placement & Routing
    • Bitstream generation
    • Analyze timing, view layout, simulation, etc.
  • Download
    • Directly to Xilinx hardware devices with unlimited reconfigurations.

Gate Arrays (GA)

Introduction

  • In view of the speed of prototyping capability, the gate array (GA) comes after the FPGA.
  • Design implementation of:
    • FPGA chip is done with user programming,
    • Gate array is done with metal mask design and processing.

Manufacturing Process

  • Gate array implementation requires a two-step manufacturing process: a) The first phase, which is based on generic (standard) masks, results in an array of uncommitted transistors on each GA chip. b) These uncommitted chips can be customized later, which is completed by defining the metal interconnects between the transistors of the array.

Characteristics

  • The GA chip utilization factor is higher than that of FPGA.
    • The used chip area divided by the total chip area.
  • Chip speed is also higher.
    • More customized design can be achieved with metal mask designs.
  • Typical gate array chips can implement millions of logic gates.

Standard Cell Based Design (Semi-Custom ASIC)

Introduction

  • One of the most prevalent design styles, also called semi-custom design style.
  • Requires developing a full custom mask set.
  • Basic idea:
    • Commonly used logic cells are developed, and stored in a standard cell library.
    • A typical library may contain a few hundred cells (Inverters, NAND gates, NOR gates, AOI gates, OAI gates, 2-to-1 MUX, D-latches, flip-flops, etc.).

Cell Characteristics

  • Each cell is designed with a fixed height.
    • To enable automated placement of the cells, and routing of inter-cell connections.
    • A number of cells can be abutted side-by-side to form rows.
  • The power and ground rails typically run parallel to upper and lower boundaries of the cell.
    • Neighboring cells share a common power and ground bus.
  • The input and output pins are located on the upper and lower boundaries of the cell.

Floorplan and Layout

  • Inside the I/O frame which is reserved for I/O cells, the chip area contains rows or columns of standard cells.
    • Between cell rows are channels for routing.
    • Over-the-cell routing is also possible.
  • The physical design and layout of logic cells ensure that:
    • When placed into rows, their heights match.
    • Neighboring cells can abut side-by-side, which provides natural connections for power and ground lines in each row.

Full-Custom Design

Introduction

  • In the full custom design, the entire mask design is done anew without use of any library.
    • The development cost of such a design style is prohibitively high.
    • The concept of design reuse is becoming popular to reduce design cycle time and cost.
  • In real full-custom layout, the geometry, orientation and placement of every transistor is done individually by the designer.

Productivity and Use Cases

  • Design productivity is usually very low (typically 10 to 20 transistors per day, per designer).
  • In digital CMOS VLSI, full-custom design is rarely used due to the high labor cost.
    • Exceptions to this include the design of high-volume products such as memory chips, high-performance microprocessors and FPGA masters.

Rigor and Hybrid Designs

  • The most rigorous full custom design can be the design of a memory cell.
    • Static or dynamic.
    • Since the same layout design is replicated, there would not be any alternative to high density memory chip design.
  • For logic chip design, a good compromise can be achieved by combining different design styles on the same chip.
    • Standard cells, data-path cells and PLAs.

Comparison Among Various Design Styles

FPGA Gate Array Standard Cell Full Custom
Cell size Fixed Fixed Fixed height Variable
Cell type Programmable Fixed Variable Variable
Cell placement Fixed Fixed In row Variable
Interconnect Programmable Variable Variable Variable
Design time Very fast Fast Medium Slow