The Verilog Design and Implementation Flow

After a digital system is described in Verilog, it undergoes a sequential process of verification and implementation to become a physical piece of hardware. This process involves simulation, synthesis, target selection, and final testing.

Step 1: Verification through Simulation

Before committing a design to hardware, its functional correctness must be rigorously verified. This is achieved through simulation.

  • The process is analogous to compiling and running a program written in a high-level software language.
  • It requires a dedicated piece of Verilog code called a test bench or test harness. The role of the test bench is to automatically apply a sequence of inputs to the design and check if the outputs match the expected behavior.

Step 2: Implementation through Synthesis

Once the design’s functionality is verified in simulation, it is ready for synthesis. This is the process of converting the abstract Verilog description into a physical hardware implementation.

  • A synthesis tool is used to automatically translate the Verilog code into a netlist, which is a detailed description of interconnected low-level primitives.
  • This netlist is then mapped onto a specific hardware technology.

Step 3: Selecting a Hardware Target

The synthesized netlist can be implemented on one of two primary types of hardware, chosen based on the project’s goals.

  • ASIC (Application Specific Integrated Circuit):
    • This is a custom chip, fully optimized for a single function.
    • It is chosen when high performance and high packing density are critical.
    • It is the standard for products manufactured in large numbers, like commercial processor chips.
  • FPGA (Field Programmable Gate Array):
    • This is a generic, programmable chip that can be configured by the designer.
    • It is chosen when a fast turnaround time is needed to validate a design.
    • The entire implementation process can be done in a laboratory with a kit and software.
    • There is generally a tradeoff in performance compared to a custom ASIC.

Step 4: Synthesis Tools and Physical Testing

The final stage involves using specific software tools to generate the hardware and then testing the physical result.

  • Synthesis Software:
    • For ASIC targets, large commercial CAD tool suites from vendors like Cadence and Synopsys are used.
    • For FPGA targets, vendor-specific software is required, such as Xilinx ISE or VIVADO for Xilinx devices.
  • Physical Hardware Testing:
    • Once the design is a physical chip, the simulation test bench is no longer used.
    • Instead, physical testing equipment is used. Signals are applied from a source like a signal generator, and the response is measured and evaluated by an oscilloscope or logic analyzer.