Verilog Operators

Operator Precedence

Verilog operators have a defined precedence which determines the order of evaluation in an expression. Parentheses can be used to change the order of evaluation.

  • Operators on the same line in the table below have the same precedence.
  • All operators associate left to right, except for the conditional operator (?:).
  • Precedence increases from the bottom of the table to the top.
Operators Description Precedence
+ - ! ~ Unary Plus, Unary Minus, Logical Negation, Bitwise Negation Highest
** Exponentiation
* / % Multiply, Divide, Modulus
+ - Binary Add, Binary Subtract
<< >> >>> Logical Shifts, Arithmetic Shift
< <= > >= Relational Operators
== != === !== Equality Operators
& ~& Bitwise AND, Bitwise NAND
^ ~^ Bitwise XOR, Bitwise XNOR
` ~ `
&& Logical AND
` `
? : Conditional Operator Lowest

Arithmetic Operators

These operators perform arithmetic operations.

  • +: Unary Plus, Binary Addition
  • -: Unary Minus, Binary Subtraction
  • *: Multiplication
  • /: Division
  • %: Modulus
  • **: Exponentiation (power)

If any bit in an operand of an arithmetic expression is x or z, the result of the entire expression will be x.

A practical example is an n-bit adder, which can be described using the addition and concatenation operators: assign {cout, sum} = in1 + in2 + cin;

Relational Operators

These operators compare two operands and return a 1-bit result: 1 for true or 0 for false.

  • >: Greater than
  • <: Less than
  • >=: Greater than or equal to
  • <=: Less than or equal to

Equality Operators

These operators compare two operands for equality. They are a special class of relational operators.

  • == (Logical Equality): Compares for equality on a bit-by-bit basis. The result is 1 if the operands are identical and 0 if they are not. If either operand contains an x or z bit, the result is x (unknown).
  • != (Logical Inequality): The logical inverse of ==.
  • === (Case Equality): Compares for equality on a bit-by-bit basis, treating x and z as valid logic states. The result is always 1 (true) or 0 (false). For a === b to be true, the operands must be identical in all bit positions, including any x and z bits.
  • !== (Case Inequality): The logical inverse of ===.

Logical Operators

These operators perform logical operations and return a single-bit value (0, 1, or x). A value of 0 is treated as logical false, while any non-zero value is treated as logical true.

  • !: Logical Negation
  • &&: Logical AND
  • ||: Logical OR

Bitwise Operators

These operators perform operations on a bit-by-bit basis between two operands.

  • ~: Bitwise NOT (unary)
  • &: Bitwise AND
  • |: Bitwise OR
  • ^: Bitwise XOR
  • ~^ or ^~: Bitwise XNOR

Reduction Operators

These are unary operators that accept a single vector operand and produce a single-bit output. They perform their corresponding bitwise operation on all bits of the vector.

  • &: Reduction AND
  • |: Reduction OR
  • ^: Reduction XOR
  • ~&: Reduction NAND
  • ~|: Reduction NOR
  • ~^: Reduction XNOR

Example: assign y = &x; where x is a 4-bit vector. This is equivalent to assign y = x[3] & x[2] & x[1] & x[0];.

Shift Operators

  • <<: Logical Shift Left. Shifts the bits of an operand to the left, filling the vacated positions with 0s.
  • >>: Logical Shift Right. Shifts the bits of an operand to the right, filling the vacated positions with 0s.
  • >>>: Arithmetic Shift Right. Shifts the bits of a signed operand to the right. For positive numbers, it fills with 0. For negative numbers, it preserves the sign by filling the vacated positions with the value of the most significant bit (MSB).

Concatenation and Replication Operators

  • { , } (Concatenation): Joins together bits from two or more comma-separated expressions to form a larger vector.
  • {n{m}} (Replication): Joins together n copies of an expression m, where n is a constant.

Example: {4'b0101, 3'b110} results in the 7-bit vector 7'b0101110. Example: {4{2'b01}} results in the 8-bit vector 8'b01010101.

Conditional Operator

The conditional (or ternary) operator provides a way to express simple if-else logic in a continuous assignment.

  • Syntax: cond_expr ? true_expr : false_expr;
  • If the cond_expr is true (non-zero), the true_expr is evaluated. If it is false (0), the false_expr is evaluated.