Main Objectives of the Course

Hardware Modeling Using Verilog

  1. Learn about the Verilog hardware description language.
  2. Understand the difference between behavioral and structural design styles.
  3. Learn to write test benches and analyze simulation results.
  4. Learn to model combinational and sequential circuits.
  5. Distinguish between good and bad coding practices.
  6. Case studies with some complex designs.

Need for Verilog and CAD in VLSI

Design complexity increasing rapidly

  • Increased size and complexity
  • Fabrication technology improving
  • CAD tools are essential
  • Conflicting requirements like area, speed, and energy consumption

The present trend

  • Standardize the design flow
  • Emphasis on low-power design, and increased performance

Need to use Computer Aided Design (CAD) tools

  • Based on Hardware Description Language (HDL).
  • HDLs provide formats for representing the outputs of various design steps.
  • A CAD tool transforms its HDL input into a HDL output that contains more detailed information about the hardware.
    • Behavioral level to register transfer level
    • Register transfer level to gate level
    • Gate level to transistor level
    • Transistor level to the layout level

VLSI Design Flow Overview

Standardized design procedure

  • Specification
  • Synthesis
  • Simulation
  • Layout
  • Testability analysis
  • and many more ……

Design Flow Sequence

  1. Design Idea: The starting point of the design process.
  2. Behavioral Design: Describes the circuit’s functionality using high-level constructs. The output is a Flow Graph or Pseudo Code.
  3. Data Path Design: Defines the bus and register architecture required to implement the behavior. The output is a Bus/Register Structure.
  4. Logic Design: Translates the data path into a network of logic gates and flip-flops. The output is a Gate/F-F Netlist.
  5. Physical Design: Involves the placement and routing of components. The output is the Transistor Layout.
  6. Manufacturing: The process of fabricating the design onto a silicon wafer.
  7. Chip / Board: The final, physical implementation of the design idea.

Design Step Outputs

This table summarizes the outputs generated at each major design stage.

Step Name Output
Behavioral Design Flow Graph, Pseudo Code
Data Path Design Bus/Register Structure
Logic Design Gate/F-F Netlist
Physical Design Transistor Layout

VLSI Design Flow Stages

Behavioral Design

  • Specify the functionality of the design in terms of its behavior.
  • Various ways of specifying:
    • Boolean expression or truth table.
    • Finite-state machine behavior (e.g., state transition diagram or table).
    • In the form of a high-level algorithm.
  • Needs to be synthesized into more detailed specifications for hardware realization.

Data Path Design

  • Generate a netlist of register transfer level components, like registers, adders, multipliers, multiplexers, decoders, etc.
  • A netlist is a directed graph, where the vertices indicate components, and the edges indicate interconnections.
  • A netlist specification is also referred to as structural design.
    • Netlist may be specified at various levels, where the components may be functional modules, gates or transistors.
    • Systematically transformed from one level to the next.

Logic Design

  • Generate a netlist of gates/flip-flops or standard cells.
  • A standard cell is a pre-designed circuit module (like gates, flip-flops, multiplexer, etc.) at the layout level.
  • Various logic optimization techniques are used to obtain a cost effective design.
  • There may be conflicting requirements during optimization:
    • Minimize number of gates.
    • Minimize number of gate levels (i.e. delay).
    • Minimize signal transition activities (i.e. dynamic power).

Physical Design and Manufacturing

  • Generate the final layout that can be sent for fabrication.
  • The layout contains a large number of regular geometric shapes corresponding to the different fabrication layers.
  • Alternatively, the final target may be Field Programmable Gate Array (FPGA), where technology mapping from the gate level netlist is used.
    • Can be programmed in-field.
    • Much greater flexibility, but less speed.

Verification and Testing

  • Simulation for verification
    • At various levels: logic level, switch level, circuit level
  • Formal verification
    • Used to verify the designs through formal techniques
  • Testability analysis and Test pattern generation
    • Required for testing the manufactured devices

Digital IC Design Flow

This flowchart outlines the primary stages of designing a digital integrated circuit (IC), separating the process into logical and physical design phases.

Logical Design (Front-end CAD)

This phase focuses on defining the circuit’s functionality and structure in an abstract, pre-layout form. The core flow is as follows: 🧠

  • Design Entry: The initial step where the design is described using a Hardware Description Language (HDL), such as Verilog or VHDL.
  • Logic Synthesis: An automated process that converts the high-level HDL description into an optimized gate-level netlist.
  • Partitioning: The process of dividing the large circuit into smaller, more manageable sub-circuits or blocks.
  • Pre-layout Simulation: This verification step is performed after synthesis to confirm the functional correctness of the gate-level netlist before beginning the time-intensive physical design stage.

Physical Design (Back-end CAD)

This phase involves transforming the abstract circuit netlist into a geometric layout that can be manufactured. The core flow is as follows: 🏗️

  • Floorplanning: The process of arranging the partitioned blocks on the chip area and allocating space for power grids and I/O pins.
  • Placement: The detailed process of finding the optimal physical locations for all the individual standard cells.
  • Routing: The process of creating the physical connections (metal wires) between the placed cells and blocks.
  • Circuit Extraction & Post-layout Simulation: In the final verification loop, physical wire details are extracted from the completed layout. A final, highly accurate Post-layout Simulation is then run to verify that the chip’s timing and power still meet requirements before it is sent for fabrication.